UM10562 Datasheet, PDF (403/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 14: LPC408x/407x USB OTG controller
14.8.8 I²C Transmit Register
This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.
I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]
are ignored for master-receive operations. The master-receiver must write a dummy byte
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is
set or the START bit is set to cause a RESTART condition on a byte written to the TX
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,
the last byte of a master-receive operation is not acknowledged.
Table 320. I²C Transmit register (I2C_TX - address 0x2008 C300) bit description
Bit Symbol Description
7:0 TX Data Transmit data.
8
START When 1, issue a START condition before transmitting this byte.
9
STOP
When 1, issue a STOP condition after transmitting this byte.
31:10 -
Reserved. Read value is undefined, only zero should be written.
Reset Value
-
-
-
-
14.8.9 I²C Status Register
The I2C_STS register provides status information on the TX and RX blocks as well as the
current state of the external buses. Individual bits are enabled as interrupts by the
I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.
Table 321. I²C status register (I2C_STS - address 0x2008 C304) bit description
Bit Symbol Value Description
Reset
Value
0
TDI
Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is
0
cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.
0 Transaction has not completed.
1 Transaction completed.
1
AFI
Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high,
0
then this I²C has lost the arbitration to another device on the bus. The Arbitration Failure
bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.
0 No arbitration failure on last transmission.
1 Arbitration failure occurred on last transmission.
2
NAI
No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an
0
acknowledge from the receiver. This bit is set if the acknowledge is not received. It is
cleared when a byte is written to the master TX FIFO.
0 Last transmission received an acknowledge.
1 Last transmission did not receive an acknowledge.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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