UM10562 Datasheet, PDF (667/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 23: LPC408x/407x I²S interface
23.5.6 DMA Configuration Register 1
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in Table 519. Refer to the General Purpose DMA Controller chapter
for details of DMA operation.
Table 519: DMA Configuration register 1 (DMA1 - address 0x400A 8014) bit description
Bit Symbol
Description
0
1
7:2
11:8
15:12
19:16
31:20
RX_DMA1_ENABLE
TX_DMA1_ENABLE
-
RX_DEPTH_DMA1
-
TX_DEPTH_DMA1
-
When 1, enables DMA1 for I²S receive.
When 1, enables DMA1 for I²S transmit.
Reserved. Read value is undefined, only zero should be written.
Set the FIFO level that triggers a receive DMA request on DMA1.
Reserved. Read value is undefined, only zero should be written.
Set the FIFO level that triggers a transmit DMA request on DMA1.
Reserved. Read value is undefined, only zero should be written.
Reset
Value
0
0
0
0
NA
0
NA
23.5.7 DMA Configuration Register 2
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in Table 514.
Table 520: DMA Configuration register 2 (DMA2 - address 0x400A 8018) bit description
Bit Symbol
Description
0
1
7:2
11:8
15:12
19:16
31:20
RX_DMA2_ENABLE
TX_DMA2_ENABLE
-
RX_DEPTH_DMA2
-
TX_DEPTH_DMA2
-
When 1, enables DMA1 for I²S receive.
When 1, enables DMA1 for I²S transmit.
Unused.
Set the FIFO level that triggers a receive DMA request on DMA2.
Reserved. Read value is undefined, only zero should be written.
Set the FIFO level that triggers a transmit DMA request on DMA2.
Reserved. Read value is undefined, only zero should be written.
Reset
Value
0
0
0
0
NA
0
NA
UM10562
User manual
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Rev. 1 — 13 September 2012
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