UM10562 Datasheet, PDF (788/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 30: LPC408x/407x Event Monitor/Recorder
30.6.3 Event Monitor/Recorder Counters Register
The Event Monitor/Recorder Counters Register is a read-only register that allows reading
counters that record the number of events on each Event Monitor/Recorder channel.
Table 661. Event Monitor/Recorder Counters Register (ERCOUNTERS - 0x4002 4088) bit description
Bit Symbol
Description
Reset
value
2:0 COUNTER0 Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there 0
if additional events occur. This counter is cleared when the corresponding EVx bit in the
ERSTATUS register is cleared by software.
7:3 -
Reserved. The value read from a reserved bit is not defined.
NA
10:8 COUNTER1 Value of the counter for event 1. See description for COUNTER0.
0
15:11 -
Reserved. The value read from a reserved bit is not defined.
NA
18:16 COUNTER2 Value of the counter for event 2. See description for COUNTER0.
0
31:19 -
Reserved. The value read from a reserved bit is not defined.
NA
30.6.4 Event Monitor/Recorder First Stamp Register
The read-only Event Monitor/Recorder First Stamp Registers record a timestamp (from
the RTC) of the first event that occurs on each Event Monitor/Recorder channel. This is
when the corresponding EVx bit in the ERSTATUS register becomes set. Once that has
happened, these registers will not change until software clears the corresponding EVx bit
in the ERSTATUS register.
Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS
register = 1.
Table 662. Event Monitor/Recorder First Stamp Register (ERFIRSTSTAMP0 - 0x0x4002 4090,
ERFIRSTSTAMP1 - 0x0x4002 4094, ERFIRSTSTAMP2 - 0x4002 4098) bit
description
Bit Symbol Description
Reset value
5:0 SEC Seconds value in the range of 0 to 59.
NA
11:6 MIN
Minutes value in the range of 0 to 59.
NA
16:12 HOUR Hours value in the range of 0 to 23.
NA
25:17 DOY Day of Year value in the range of 1 to 366.
NA
31:26 -
Reserved. The value read from a reserved bit is not defined.
NA
30.6.5 Event Monitor/Recorder Last Stamp Register
The read-only Event Monitor/Recorder Last Stamp Registers record a timestamp (from
the RTC) whenever an event occurs on each Event Monitor/Recorder channel.
Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS
register = 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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