UM10562 Datasheet, PDF (371/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 12: LPC408x/407x USB device controller
UDCA
0
1
2
DDP-EP2
NULL
NULL
Next_DD_pointer
DD-EP2-a
Next_DD_pointer
DD-EP2-b
Next_DD_pointer
DD-EP2-c
NULL
UDCA HEAD
REGISTER
NULL
16
DDP-EP16
Next_DD_pointer
DD-EP16-a
Next_DD_pointer
DD-EP16-b
NULL
31
DDP-EP31
Fig 44. UDCA Head register and DMA Descriptors
12.15.3 Triggering the DMA engine
An endpoint raises a DMA request when Slave mode is disabled by setting the
corresponding bit in the EpIntEn register to 0 (Section 12.10.3.2) and an endpoint
interrupt occurs (see Section 12.10.7.1 “USB DMA Request Status register”).
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
EpDMASt, the corresponding bit in DMARSt is set, and a valid DD is found for the
endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in DMARSt, the endpoint with the lowest physical endpoint
number is processed first.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section 12.12.3).
12.15.4 The DMA descriptor
DMA transfers are described by a data structure called the DMA Descriptor (DD).
DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at
word-aligned addresses.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
The parameters associated with a DMA transfer are:
• The start address of the DMA buffer
• The length of the DMA buffer
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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