UM10562 Datasheet, PDF (687/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 24: LPC408x/407x Timer0/1/2/3
24.6 Register description
Each Timer/Counter contains the registers shown in Table 534 ("Reset Value" refers to the
data stored in used bits only; it does not include reserved bits content). More detailed
descriptions follow.
Table 534. Register overview: Timer0/1/2/3 (register base addresses 0x4000 4000 (TIMER0), 0x4000 8000 (TIMER1),
0x4009 0000 (TIMER2), 0x4009 4000 (TIMER3))
Name
Access Address Description
offset
Reset Section
value^[1]
IR
R/W 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR
0
Table 535
can be read to identify which of eight possible interrupt sources are
pending.
TCR
R/W 0x004 Timer Control Register. The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset
through the TCR.
0
Table 536
TC
R/W 0x008 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of
0
Table 537
PCLK. The TC is controlled through the TCR.
PR
R/W 0x00C Prescale Register. When the Prescale Counter (PC) is equal to this
0
Table 538
value, the next clock increments the TC and clears the PC.
PC
R/W 0x010 Prescale Counter. The 32 bit PC is a counter which is incremented
0
Table 539
to the value stored in PR. When the value in PR is reached, the TC
is incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
MCR
R/W 0x014 Match Control Register. The MCR is used to control if an interrupt
0
Table 540
is generated and if the TC is reset when a Match occurs.
MR0
R/W 0x018 Match Register 0. MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt
every time MR0 matches the TC.
0
Table 541
MR1
R/W 0x01C Match Register 1. See MR0 description.
0
Table 541
MR2
R/W 0x020 Match Register 2. See MR0 description.
0
Table 541
MR3
R/W 0x024 Match Register 3. See MR0 description.
0
Table 541
CCR
R/W 0x028 Capture Control Register. The CCR controls which edges of the
0
Table 542
capture inputs are used to load the Capture Registers and whether
or not an interrupt is generated when a capture takes place.
CR0
RO
0x02C Capture Register 0. CR0 is loaded with the value of TC when there
0
Table 543
is an event on the CAPn.0 input.
CR1
RO
0x030 Capture Register 1. See CR0 description.
0
Table 543
EMR
R/W 0x03C External Match Register. The EMR controls the external match
pins.
0
Table 544
CTCR
R/W 0x070 Count Control Register. The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and
edge(s) for counting.
0
Table 546
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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