UM10562 Datasheet, PDF (919/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 41: Supplementary information
- 0x400B 806C) bit description . . . . . . . . . . . .741
Table 591. MCPWM Interrupt Flags clear address
(INTF_CLR - 0x400B 8070) bit description. . .742
Table 592. MCPWM Capture clear address (CAP_CLR -
0x400B 8074) bit description . . . . . . . . . . . . .742
Table 593. Encoder states . . . . . . . . . . . . . . . . . . . . . . . .751
Table 594. Encoder state transitions^[1] . . . . . . . . . . . . . .751
Table 595. Encoder direction . . . . . . . . . . . . . . . . . . . . .752
Table 596. QEI pin description. . . . . . . . . . . . . . . . . . . . .754
Table 597. Register overview: QEI (base address 0x400B
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .755
Table 598: QEI Control register (CON - address
0x400B C000) bit description . . . . . . . . . . . . .756
Table 599: QEI Configuration register (CONF - address
0x400B C008) bit description . . . . . . . . . . . . .756
Table 600: QEI Status register (STAT - address
0x400B C004) bit description . . . . . . . . . . . . .756
Table 601: QEI Position register (POS - address
0x400B C00C) bit description . . . . . . . . . . . . .757
Table 602: QEI Maximum Position register (MAXPOS -
address 0x400B C010) bit description . . . . . .757
Table 603: QEI Position Compare register 0 (CMPOS0 -
address 0x400B C014) bit description . . . . . .757
Table 604: QEI Position Compare register 1 (CMPOS1 -
address 0x400B C018) bit description . . . . . .757
Table 605: QEI Position Compare register 2 (CMPOS2 -
address 0x400B C01C) bit description . . . . . .758
Table 606: QEI Index Count register (INXCNT - address
0x400B C020) bit description . . . . . . . . . . . . .758
Table 607: QEI Index Compare register 0 (INXCMP0 -
address 0x400B C024) bit description . . . . . .758
Table 608: QEI Timer Load register (LOAD - address
0x400B C028) bit description . . . . . . . . . . . . .758
Table 609: QEI Timer register (TIME - address
0x400B C02C) bit description . . . . . . . . . . . . .758
Table 610: QEI Velocity register (VEL - address
0x400B C030) bit description . . . . . . . . . . . . .759
Table 611: QEI Velocity Capture register (CAP - address
0x400B C034) bit description . . . . . . . . . . . . .759
Table 612: QEI Velocity Compare register (VELCOMP -
address 0x400B C038) bit description . . . . . .759
Table 613: QEI Digital Filter ON PHA (FILTERPHA - address
0x400B C03C) bit description . . . . . . . . . . . . .759
Table 614: QEI Digital Filter on PHB (FILTERPHB - address
0x400B C040) bit description . . . . . . . . . . . . .759
Table 615: QEI Digital Filter on INX (FILTERINX - address
0x400B C044) bit description . . . . . . . . . . . . .760
Table 616: QEI index acceptance Window (WINDOW -
address 0x400B C048) bit description . . . . . .760
Table 617: QEI Index Compare register 1 (INXCMP1 -
address 0x400B C04C) bit description . . . . . .760
Table 618: QEI Index Compare register 2 (INXCMP2 -
address 0x400B C050) bit description . . . . . .760
Table 619: QEI Interrupt Status register (INTSTAT - address
0x400B CFE0) bit description . . . . . . . . . . . . .761
Table 620: QEI Interrupt Set register (SET - address
0x400B CFEC) bit description . . . . . . . . . . . .762
Table 621: QEI Interrupt Clear register (CLR -
0x400B CFE8) bit description . . . . . . . . . . . . 763
Table 622: QEI Interrupt Enable register (IE - address
0x400B CFE4) bit description . . . . . . . . . . . . 764
Table 623: QEI Interrupt Enable Set register (IES - address
0x400B CFDC) bit description . . . . . . . . . . . . 765
Table 624: QEI Interrupt Enable Clear register (IEC - address
0x400B CFD8) bit description . . . . . . . . . . . . 766
Table 625. RTC pin description. . . . . . . . . . . . . . . . . . . . 769
Table 626. Register overview: Real-Time Clock (base
address 0x4002 4000) . . . . . . . . . . . . . . . . . . 770
Table 627. Interrupt Location Register (ILR - address
0x4002 4000) bit description . . . . . . . . . . . . . 771
Table 628. Clock Control Register (CCR - address
0x4002 4008) bit description . . . . . . . . . . . . . 771
Table 629. Counter Increment Interrupt Register (CIIR -
address 0x4002 400C) bit description . . . . . . 772
Table 630. Alarm Mask Register (AMR - address
0x4002 4010) bit description . . . . . . . . . . . . . 772
Table 631. RTC Auxiliary control register (RTC_AUX -
address 0x4002 405C) bit description . . . . . . 773
Table 632. RTC Auxiliary Enable register (RTC_AUXEN -
address 0x4002 4058) bit description . . . . . . 773
Table 633. Consolidated Time register 0 (CTIME0 - address
0x4002 4014) bit description . . . . . . . . . . . . . 774
Table 634. Consolidated Time register 1 (CTIME1 - address
0x4002 4018) bit description . . . . . . . . . . . . . 774
Table 635. Consolidated Time register 2 (CTIME2 - address
0x4002 401C) bit description . . . . . . . . . . . . . 774
Table 636. Time Counter relationships and values . . . . . 774
Table 637. Time Counter registers . . . . . . . . . . . . . . . . . 775
Table 638. Seconds register (SEC - address 0x4002 4020)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 775
Table 639. Minutes register (MIN - address 0x4002 4024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Table 640. Hours register (HRS - address 0x4002 4028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Table 641. Day of month register (DOM - address
0x4002 402C) bit description . . . . . . . . . . . . . 776
Table 642. Day of week register (DOW - address
0x4002 4030) bit description . . . . . . . . . . . . . 776
Table 643. Day of year register (DOY - address
0x4002 4034) bit description . . . . . . . . . . . . . 776
Table 644. Month register (MONTH - address 0x4002 4038)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 776
Table 645. Year register (YEAR - address 0x4002 403C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Table 646. Calibration register (CALIBRATION - address
0x4002 4040) bit description . . . . . . . . . . . . . 777
Table 647. General purpose registers (GPREG[0:4] -
addresses 0x4002 4044 (GPREG0) to
0x4002 4054 (GPREG4)) bit description . . . . 778
Table 648. Alarm registers . . . . . . . . . . . . . . . . . . . . . . . 778
Table 649. Alarm Seconds register (ASEC - address
0x4002 4060) bit description . . . . . . . . . . . . . 778
Table 650. Alarm Minutes register (AMIN - address
0x4002 4064) bit description . . . . . . . . . . . . . 778
Table 651. Alarm Hours register (AHRS - address
0x4002 4068) bit description . . . . . . . . . . . . . 779
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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