UM10562 Datasheet, PDF (899/942 Pages) NXP Semiconductors – LPC408x/407x User manual

UM10562
Chapter 39: LPC408x/407x JTAG, Debug, and Trace
Rev. 1 — 13 September 2012
User manual
39.1 Features
• Supports both standard JTAG and ARM Serial Wire Debug modes.
• Direct debug access to all memories, registers, and peripherals.
• No target resources are required for the debugging session.
• Trace port provides CPU instruction trace capability.
• Eight Breakpoints. Six instruction breakpoints that can also be used to remap
instruction addresses for code patches. Two data comparators that can be used to
remap addresses for patches to literal values.
• Four data Watchpoints that can also be used as trace triggers.
• Instrumentation Trace Macrocell allows additional software controlled trace capability.
39.2 Introduction
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watchpoints.
39.3 Description
Debugging with the LPC408x/407x defaults to JTAG. Once in the JTAG debug mode, the
debug tool can switch to Serial Wire Debug mode.
Instruction trace is supported by a 4-bit parallel interface using 5 pins. Note that the trace
function available for the Cortex-M4 is functionally very different than the trace that was
available for previous ARM7 based devices, using only 5 pins instead of 10.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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