UM10562 Datasheet, PDF (386/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 13: LPC408x/407x USB Host controller
13.3 Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller, and I²C interface. The
I²C interface controls the external OTG ATX.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Table 308. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
AHB
Advanced High-Performance Bus
ATX
Analog Transceiver
DMA
Direct Memory Access
FS
Full Speed
LS
Low Speed
OHCI
Open Host Controller Interface
USB
Universal Serial Bus
13.3.1 Features
• OHCI compliant.
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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