UM10562 Datasheet, PDF (629/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 22: LPC408x/407x I2C-bus interfaces
22.8.7 I²C Slave Address registers
These registers are readable and writable and are only used when an I²C interface is set
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contain 0x00, the I²C will not acknowledge any address on the bus. All
four registers will be cleared to this disabled state on reset.
Table 498. I²C Slave Address register 0 (ADR0 - address 0x4001 C00C (I2C0), 0x4005 C00C
(I2C1), 0x400A 000C (I2C2)) bit description
Bit Symbol Description
Reset value
0 GC
General Call enable bit.
0
7:1 Address The I²C device address for slave mode.
0x00
31:8 -
Reserved. The value read from a reserved bit is not defined.
-
Table 499. I²C Slave Address registers (ADR[1:3] - address 0x4001 C020 (ADR1) to
0x4001 C028 (ADR3) (I2C0), 0x4005 C020 (ADR1) to 0x4005 C028 (ADR3) (I2C1),
0x400A 0020 (ADR1) to 0x400A 0028 (ADR3) (I2C2)) bit description
Bit Symbol Description
Reset value
0
GC
General Call enable bit.
0
7:1 Address The I²C device address for slave mode.
0x00
31:8 -
Reserved. The value read from a reserved bit is not defined.
-
22.8.8 I²C Mask registers
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADRn register associated with that mask
register. In other words, bits in an I2ADRn register which are masked are not taken into
account in determining an address match.
The mask register has no effect on comparison to the General Call address (“0000000”).
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine which received address actually caused the match.
Table 500. I²C Mask registers (MASK[0:3] - address 0x4001 C030 (MASK0) to 0x4001 C03C
(MASK3) (I2C0), 0x4005 C030 (MASK0) to 0x4005 C03C (MASK3) (I2C1),
0x400A 0030 (MASK0) to 0x400A 003C (MASK3) (I2C1)) bit description
Bit Symbol Description
Reset value
0-
Reserved. User software should not write ones to reserved bits.
0
This bit reads always back as 0.
7:1 MASK Mask bits.
0x00
31:8 -
Reserved. The value read from a reserved bit is not defined.
-
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
629 of 942