UM10562 Datasheet, PDF (196/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.14 External memory interface
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding EMCStaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
the A1 and/or A0 lines to provide address or non-address function is accomplished using
the IOCON registers (see Section 7.4.1).
Symbol "a_b" in the following figures refers to the highest order address line in the data
bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the
external memory interface.
9.14.1 32-bit wide memory bank connection
CS
OE
BLS[3]
D[31:24]
A[a_b:2]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[2]
D[23:16]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[1]
D[15:8]
CE
OE
WE
IO[7:0]
A[a_m:0]
a. 32 bit wide memory bank interfaced to four 8 bit memory chips
CS
OE
WE
BLS[3]
BLS[2]
D[31:16]
A[a_b:2]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
BLS[1]
BLS[0]
D[15:0]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
b. 32 bit wide memory bank interfaced to two 16 bit memory chips
BLS[0]
D[7:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
UM10562
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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