UM10562 Datasheet, PDF (142/942 Pages) NXP Semiconductors – LPC408x/407x User manual

UM10562
Chapter 8: LPC408x/407x GPIO
Rev. 1 — 13 September 2012
User manual
8.1 Basic configuration
GPIOs are configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCGPIO. This enables the
GPIOs themselves, GPIO interrupts, and the IOCON block.
2. Pins: See Section 7.4.1 for GPIO pins and their modes.
3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see
(Section 3.12.8).
4. Interrupts: Enable GPIO interrupts in EnR (Table 104 or Table 109) and EnF
(Table 105 or Table 110). Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register.
8.2 Features
8.2.1 Digital I/O ports
• Accelerated GPIO functions:
– GPIO registers are located on a peripheral AHB bus for fast I/O timing.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte, half-word, and word addressable.
– Entire port value can be written in one instruction.
– GPIO registers are accessible by the GPDMA.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• All GPIO registers support bit-banding operations by the CPU.
• GPIO registers are accessible by the GPDMA controller to allow DMA of data to or
from GPIOs, synchronized to any DMA request.
• Direction control of individual port bits.
• All I/Os default to input with pull-up after reset.
UM10562
User manual
8.2.2 Interrupt generating digital ports
• Port 0 and Port 2 can provide a single interrupt for any combination of port pins.
• Each port pin can be programmed to generate an interrupt on a rising edge, a falling
edge, or both.
• Edge detection is asynchronous, so it may operate when clocks are not present, such
as during Power-down mode. With this feature, level triggered interrupts are not
needed.
• Each enabled interrupt contributes to a wake-up signal that can be used to bring the
part out of Power-down mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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