UM10562 Datasheet, PDF (540/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 20: LPC408x/407x CAN controller
• Nested Vectored Interrupt Controller (NVIC)
• CAN Transceiver
• Common Status Registers
APB BUS
NVIC
COMMON
STATUS
REGISTER
ACCEPTANCE
FILTER
INTERFACE
MANAGEMENT
LOGIC
TRANSMIT
BUFFERS 1,2
AND 3
RECEIVE
BUFFERS 1
AND 2
CAN CORE
BLOCK
ERROR
MANAGEMENT
LOGIC
BIT
TIMING
LOGIC
BIT
STREAM
PROCESSOR
TX
CAN
RX
TRANSCEIVER
Fig 79. CAN controller block diagram
20.5.1 APB Interface Block (AIB)
The APB Interface Block provides access to all CAN Controller registers.
20.5.2 Interface Management Logic (IML)
The Interface Management Logic interprets commands from the CPU, controls internal
addressing of the CAN Registers and provides interrupts and status information to the
CPU.
20.5.3 Transmit Buffers (TXB)
The TXB represents a Triple Transmit Buffer, which is the interface between the Interface
Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is
able to store a complete message which can be transmitted over the CAN network. This
buffer is written by the CPU and read out by the BSP.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
540 of 942