UM10562 Datasheet, PDF (915/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 41: Supplementary information
0x4000 C030 (UART0), 0x4009 8030 (UART2),
0x4009 C030 (UART3)) bit description. . . . . .506
Table 403: UARTn RS485 Control register (RS485CTRL -
address 0x4000 C04C (UART0), 0x4009 804C
(UART2), 0x4009 C04C (UART3)) bit description
507
Table 404. UARTn RS-485 Address Match register
(RS485ADRMATCH - address 0x4000 C050
(UART0), RS485ADRMATCH - 0x4009 8050
(UART2), RS485ADRMATCH - 0x4009 C050
(UART3)) bit description . . . . . . . . . . . . . . . . .507
Table 405. UARTn RS-485 Delay value register (RS485DLY
- address 0x4000 0054 (UART0), RS485DLY -
0x4009 8054 (UART2), RS485DLY -
0x4009 C054 (UART3)) bit description. . . . . .508
Table 406: UART4 Pin description. . . . . . . . . . . . . . . . . .512
Table 407. Register overview: UART4 (base address:
0x400A 4000) . . . . . . . . . . . . . . . . . . . . . . . . .513
Table 408: UART4 Receiver Buffer Register when DLAB = 0
(RBR - address 0x400A 4000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .514
Table 409: UART4 Transmit Holding Register when
DLAB = 0 (THR -address 0x400A 4000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .514
Table 410: UART4 Divisor Latch LSB register when
DLAB = 1 (DLL - address 0x400A 4000 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .515
Table 411: UART4 Divisor Latch MSB register when
DLAB = 1 (DLM - address 0x400A 4004 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .515
Table 412: UART4 Interrupt Enable Register when DLAB = 0
(IER - address 0x400A 4004 ) bit description .516
Table 413: UART4 Interrupt Identification Register (IIR -
address 0x400A 4008) bit description . . . . . .517
Table 414: UART4 Interrupt Handling . . . . . . . . . . . . . . .518
Table 415: UART4 FIFO Control Register (FCR - address
0x400A 4008) bit description . . . . . . . . . . . . .520
Table 416: UART4 Line Control Register (LCR - address
0x400A 400C) bit description . . . . . . . . . . . . .521
Table 417: UART4 Line Status Register (LSR - address
0x400A 4014) bit description . . . . . . . . . . . . .522
Table 418: UART4 Scratch Pad Register (SCR - address
0x400A 401C) bit description . . . . . . . . . . . . .523
Table 419: UART4 Auto-baud Control Register (ACR -
0x400A 4020) bit description . . . . . . . . . . . . .524
Table 420: UART4 IrDA Control Register (ICR - address
0x400A 4024) bit description . . . . . . . . . . . . .527
Table 421: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . .527
Table 422: UART4 Fractional Divider Register (FDR -
address 0x400A 4028) bit description . . . . . .528
Table 423. Fractional Divider setting look-up table . . . . .530
Table 424. UART4 Oversampling Register (OSR - address
0x400A 402C) bit description . . . . . . . . . . . . .531
Table 425. UART4 Smart Card Interface Control register
(SCICTRL - address 0x400A 4048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .532
Table 426: UART4 RS485 Control register (RS485CTRL -
address 0x400A 404C) bit description . . . . . .533
Table 427. UART4 RS-485 Address Match register
(RS485ADRMATCH - address 0x400A 4050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Table 428. UART4 RS-485 Delay value register (RS485DLY
- address 0x400A 4054) bit description . . . . . 534
Table 429. UART4 Synchronous mode control register
(SYNCCTRL - address 0x400A 4058) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 430. CAN Pin descriptions . . . . . . . . . . . . . . . . . . 539
Table 431. Memory map of the CAN block . . . . . . . . . . . 544
Table 432. Register overview: CAN acceptance filter (base
address 0x4003 C000). . . . . . . . . . . . . . . . . . 544
Table 433. Register overview: central CAN (base address
0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 544
Table 434. Register overview: CAN (base address 0x4004
4000 (CAN1) and 0x4004 8000 (CAN2)) . . . . 544
Table 435. CAN1 and CAN2 controller register
summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Table 436. Register overview: CAN Wake and Sleep (base
address 0x400F C000) . . . . . . . . . . . . . . . . . 546
Table 437. CAN Mode register (CAN1MOD - address
0x4004 4000, CAN2MOD - address
0x4004 8000) bit description . . . . . . . . . . . . . 547
Table 438. CAN Command Register (CAN1CMR - address
0x4004 4004, CAN2CMR - address 0x4004 8004)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 549
Table 439. CAN Global Status Register (CAN1GSR -
address 0x4004 4008, CAN2GSR - address
0x4004 8008) bit description . . . . . . . . . . . . . 550
Table 440. CAN Interrupt and Capture Register (CAN1ICR -
address 0x4004 400C, CAN2ICR - address
0x4004 800C) bit description . . . . . . . . . . . . 553
Table 441. CAN Interrupt Enable Register (CAN1IER -
address 0x4004 4010, CAN2IER - address
0x4004 8010) bit description . . . . . . . . . . . . . 556
Table 442. CAN Bus Timing Register (CAN1BTR - address
0x4004 4014, CAN2BTR - address 0x4004 8014)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 557
Table 443. CAN Error Warning Limit register (CAN1EWL -
address 0x4004 4018, CAN2EWL - address
0x4004 8018) bit description . . . . . . . . . . . . . 558
Table 444. CAN Status Register (CAN1SR - address
0x4004 401C, CAN2SR - address 0x4004 801C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 559
Table 445. CAN Receive Frame Status register (CAN1RFS -
address 0x4004 4020, CAN2RFS - address
0x4004 8020) bit description . . . . . . . . . . . . . 560
Table 446. CAN Receive Identifier register (CAN1RID -
address 0x4004 4024, CAN2RID - address
0x4004 8024) bit description . . . . . . . . . . . . . 561
Table 447. RX Identifier register when FF = 1 . . . . . . . . 561
Table 448. CAN Receive Data register A (CAN1RDA -
address 0x4004 4028, CAN2RDA - address
0x4004 8028) bit description . . . . . . . . . . . . . 562
Table 449. CAN Receive Data register B (CAN1RDB -
address 0x4004 402C, CAN2RDB - address
0x4004 802C) bit description . . . . . . . . . . . . . 562
Table 450. CAN Transmit Frame Information register
UM10562
User manual
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Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
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