UM10562 Datasheet, PDF (624/942 Pages) NXP Semiconductors – LPC408x/407x User manual

NXP Semiconductors
UM10562
Chapter 22: LPC408x/407x I2C-bus interfaces
Table 491. Register overview: I2C-bus interface (base address 0x4001 C000 (I2C0), 0x4005 C000 (I2C1), 0x400A 0000
(I2C2))
Name
Access Address Description
offset
Reset Table
value^[1]
MASK1
R/W 0x034 I2C Slave address mask register 1. This mask register is associated 0x00 500
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
MASK2
R/W 0x038 I2C Slave address mask register 2. This mask register is associated 0x00 500
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
MASK3
R/W 0x03C I2C Slave address mask register 3. This mask register is associated 0x00 500
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
22.8.1 I²C Control Set register
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I²C interface. Writing a one to a bit of this register causes the
corresponding bit in the I²C control register to be set. Writing a zero has no effect.
Reading this register provides the current values of the control and flag bits.
Table 492. I²C Control Set register (CONSET - addresses 0x4001 C000 (I2C0), 0x4005 C000
(I2C1) , 0x400A 0000 (I2C2)) bit description
Bit Symbol Description
Reset value
1:0 -
Reserved. Read value is undefined, only zero should be written.
NA
2
AA
Assert acknowledge flag.
0
3
SI
I²C interrupt flag.
0
4
STO
STOP flag.
0
5
STA
START flag.
0
6
I2EN I²C interface enable.
0
31:7 -
Reserved. Read value is undefined, only zero should be written.
NA
I2EN I²C Interface Enable. When I2EN is 1, the I²C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I²C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I²C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I²C-bus since, when I2EN is reset, the
I²C-bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I²C interface to enter master mode and
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
When STA is 1 and the I²C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I²C interface is
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User manual
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Rev. 1 — 13 September 2012
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