BUK3F00-50WDXX Datasheet, PDF (45/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 35. Registers for mask options …continued
Register Name
Description
-
NXIFSC_CH6
-
NXIFSC_CH7
-
HL_CH0
channel 6 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
channel 7 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
channel 0 FET configuration (high or low side)
-
HL_CH1
channel 1 FET configuration (high or low side)
-
HL_CH2
channel 2 FET configuration (high or low side)
-
HL_CH3
channel 3 FET configuration (high or low side)
-
HL_CH4
channel 4 FET configuration (high or low side)
-
HL_CH5
channel 5 FET configuration (high or low side)
-
HL_CH6
channel 6 FET configuration (high or low side)
-
HL_CH7
channel 7 FET configuration (high or low side)
-
FIXED_GATE_SLEW_RATE rising and falling slew rate to have fixed or variable values
during gate turn-on
Setting required
only high side
available
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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