BUK3F00-50WDXX Datasheet, PDF (21/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 13. FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit
description …continued
Address Register
Bit Description
1Bh
IFSC_CH74^[1]
set I_{meas(ADC)(fs)} data bits in channels 7 to 4 to
one of four current trip levels:
00 = 0.5 mA
01 = 1.0 mA
10 = 1.5 mA
11 = 2.0 mA
7, 6 set channel 7 full-scale current bits 1 and 0
5, 4 set channel 6 full-scale current bits 1 and 0
3, 2 set channel 5 full-scale current bits 1 and 0
1, 0 set channel 4 full-scale current bits 1 and 0
1Ch to
23h
25h
CURR_TRIPLEV_CHn^[1]
CURR_TRIP_BLANKTIME
7 to 0 overcurrent trip threshold in channels 7 to 0;
each bit represents I_{meas(ADC)(fs)} / 255
7, 6 not used: must be set to logic 0
5 to 0 set overcurrent trip blanking time; see Table 14
[1] A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
Table 14. Overcurrent low trip blanking time
Blanking
Value
Time
Value
Time
Value
00h
0 ms
0Ch
0.51 ms 18h
01h
0.08 ms 0Dh
0.64 ms 19h
02h
0.10 ms 0Eh
0.77 ms 1Ah
03h
0.11 ms 0Fh
0.90 ms 1Bh
04h
0.13 ms 10h
1.0 ms 1Ch
05h
0.16 ms 11h
1.3 ms 1Dh
06h
0.19 ms 12h
1.5 ms 1Eh
07h
0.22 ms 13h
1.8 ms 1Fh
08h
0.26 ms 14h
2.0 ms 20h
09h
0.32 ms 15h
2.6 ms 21h
0Ah
0.38 ms 16h
3.1 ms 22h
0Bh
0.45 ms 17h
3.6 ms 23h
Time
4.1 ms
5.1 ms
6.1 ms
7.2 ms
8.2 ms
10 ms
12 ms
14 ms
16 ms
20 ms
25 ms
29 ms
Value
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Time
33 ms
41 ms
49 ms
57 ms
66 ms
82 ms
98 ms
115 ms
131 ms
164 ms
197 ms
229 ms
9.5.3 Gate inductive ring-off clamp
For high-side switches an inductive ring-off clamp can provide gate-source voltage to
allow conduction through the FET. This protects the FET by reducing the possibility of high
drain-source voltages when turning off current to an inductive load. The gate is initially set
to the source voltage to turn the FET off. During turn-off an inductive load will force the
source voltage negative and the gate will follow this until the voltage between gate and
ground reaches the inductive ring-off clamping voltage V_CL. As the source voltage
continues negative, the gate-to-source voltage will increase, turning the FET on and
allowing conduction through the FET and preventing excessive voltage between drain and
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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