BUK3F00-50WDXX Datasheet, PDF (28/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
11. Diagnostic functions
11.1 Reset for interrupt and SPI watchdog
An interrupt or SPI watchdog time-out can be reset by writing to the relevant write-only
register. Values are not stored and cannot be read back.
Table 20. Write-only (for reset) registers (addresses 29h, 2Ah) bit description
Address Register
Bit Description
29h
CLEAR_CHAN_INTN 7 to 0 clears all channels (7 to 0) and interrupt:
writing any value other than 00h to this register
clears the interrupt and ISR register
writing a logic 1 to any bit in this register clears the
interrupt and ISR register AND clears the trip latch
(resetting the retry register) for that specific channel
2Ah
CLEAR_WD
7 to 0 clear watchdog state:
writing any value to this register clears SPI Watchdog
mode
11.2 Diagnostic data
Diagnostic data can be obtained by reading data from the relevant 16-bit read-only
registers. Send the register address as data to register READBACK (27h).
Table 21.
Address
30h
31h
Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description
Register
Bit
Description
Bit latches
DIAG_BASIC
basic diagnostics
[1]
15, 14 channel 7 basic diagnostics
13, 12 channel 6 basic diagnostics
11, 10 channel 5 basic diagnostics
9, 8
channel 4 basic diagnostics
7, 6
channel 3 basic diagnostics
5, 4
channel 2 basic diagnostics
3, 2
channel 1 basic diagnostics
1, 0
channel 0 basic diagnostics
DIAG_CTRL
controller diagnostics
15
SPI error: wrong number of bits
yes^[2]
14
V_BAT low
13
SPI error: invalid address
yes^[3][4]
yes^[2]
12
charge pump fault
yes^[3][4]
11
not used
10
logic reset has occurred
yes^[3]
9
watchdog time-out has occurred
yes^[3]
8
watchdog is enabled
7 to 0 channel configuration:
1 = high side
0 = low side
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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