BUK3F00-50WDXX Datasheet, PDF (17/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
The PWM frequency can be monitored by making this an output on pin PWMMON. This is
a controller setting; see Section 9.5.5 “Controller settings”.
9.3.5 Interrupt
An interrupt can be generated to notify a controller of an error condition. An interrupt will
set pin INTN = LOW. Register settings define which faults can generate an interrupt and
which FET channels can generate an interrupt for these faults.
Table 10. Interrupt setting registers (addresses 24h, 28h) bit description
Address Register
Bit
Description
24h
IRQ_MAP^[1]
interrupt request mapping; for each bit:
1 = INTN active
0 = INTN not active
7
invalid SPI communication
6
open-circuit
5
controller fault (charge pump fault or V_BAT low)
4
temperature sensor diode open-circuit
3
watchdog time-out
2
channel overcurrent (threshold reached or exceeded)
1
channel overtemperature (threshold exceeded)
0
channel tripped under fault condition
28h
IRQ_CHAN_MAP^[1] 7 to 0 interrupt generation in individual channels 7 to 0:
1 = selected channel can generate interrupt
0 = selected channel cannot generate interrupt
[1] A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
When an interrupt is generated, data in the interrupt status register will indicate the cause.
See Section 11.1 “Reset for interrupt and SPI watchdog” for details of reading and
clearing interrupt data.
9.4 Current measurement
The current measurement is able to monitor the current from the sense connections of the
TrenchPLUS FETs. This is achieved by using one current measurement circuit for each
channel. The current measurement circuits control conditions at the sense pin of each
FET channel and can produce either an analog or digital measurement output. The digital
output can be read by a controller.
The current measurement circuit monitors the sense current according to the sense ratio
of the TrenchPLUS FET. This ratio is only valid when the sense and main FETs of the
TrenchPLUS device are fully active with V_GS at about 4 V or greater, and with the same
V_GS.
9.4.1 Current measurement circuits
For FET channels configured as high-side switches, the sense current is pulled from the
sense connection. This current is adjusted until the voltage measured at the FET pin
kelvin is the same as that measured at the FET pin sense. Since the main and sense
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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