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| BUK3F00-50WDXX Datasheet, PDF (31/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs | |||
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NXP Semiconductors
12. Application design-in information
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Cstg
Cflt(CP)
Rflt(CP)
Cflt(CP)
supply
VOLTAGE
REGULATOR
Rflt
Cp
Cmod
VCC(MOD)
VCC(DIGC)
Cflt
ANODE
GATE
Cgate(comp)
VCC(LOG)EXT
RINTN RWDTON
SENSE
KELVIN
ENABLE
WDEN
MICRO-
TIMEOUT
WDTON BUK3F00-
CONTROLLER RESET
EN
50WDxx
RL
INTERRUPT
INTN
VBAT
Crf
TrenchPLUS
FET (8Ã)
Crf
serial
periheral
interface
ENABLE
CLOCK
DATA OUT
DATA IN
SUPPLY
A/D MEASURE
ground
SCSN
SCLK
SDI
SDO
PWMMON
VCC(MEASC)
IMEAS
RIMEAS
IREFCURR
IREFTEMP
RIREFTEMP RIREFCURR
ensure potential
between grounds < 0.5 V
Fig 8. Application schematic
001aaf240
BUK3F00-50WDXX_4
Product data sheet
The charge pump pin VBAT(CP) can be connected in any one of the following ways:
⢠Connected directly to pin VBAT and the battery supply.
⢠Connected through the internal resistor to pin VBAT and the battery supply.
⢠Connected through the internal resistor to pin VBAT and a ï¬lter circuit to the battery
supply (as shown in Figure 8).
The method used depends on how important reducing the effect of charge pump noise is
for the application circuit.
Rev. 04 â 4 September 2008
© NXP B.V. 2008. All rights reserved.
31 of 52
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