BUK3F00-50WDXX Datasheet, PDF (42/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 34. Protection circuits characteristics …continued
V_BAT = V_CC(MOD) = 13 V; typical values are given at T_amb = 25 °C; limit values are given at T_case = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
I_det(oc)off
off-state open-circuit
detection current
V_KELVIN = 2.5 V
type 50WDFE
40
-
100
µA
other 50WDxx types
55
-
115
µA
V_det(oc)off
off-state open-circuit
detection voltage
2.4
2.6 2.8
V
[1] Nominal trip voltages quoted for each level. Refer to data sheet for TrenchPLUS FET devices for equivalent temperature measurement.
[2] If measured without a FET, then connect a suitable resistor between pins V_BAT and SENSE to ensure stability.
[3] Accuracy ensured when V_BAT and V_CC(MOD) > 9 V.
[4] Nominal I_trip = n × I_{meas(ADC)(fs)}, where n is the OCH and TONOCH trip level ratio for the product type; see NXIFSC_CHn in Table 19.
[5] Until the channel is fully turned on, when voltage from battery to pin KELVIN < V_{th(on)(bat-KEL)}.
[6] V_SENSE = 3.5 V for type 50WDFY, V_SENSE = 2.5 V for other 50WDxx types.
[7] Relative blanking time variation does not include clock frequency variation.
17. Application information
17.1 ElectroMagnetic Compatibility guidelines
In some applications, problems associated with electromagnetic interference can occur,
such as false overcurrent tripping, false overtemperature tripping or unexpected turn-on of
individual channels. Vulnerable points can be where currents are induced from wiring
harness connectors positioned close to sensitive control tracks (such as control lines or
FET gate, sense and kelvin lines). Good PCB and circuit design, following RF design
principles, can ensure such problems are avoided. The following guidelines are provided
to achieve this.
17.1.1 Ground layers
In multilayer PCB design, keep sensitive analog signals on the top PCB layer with a
second ground layer acting as a shield. There should be no slits or breaks in this ground
layer.
17.1.2 Circuit loops and tracks
Keep the area of circuit loops small and the length of sensitive tracks short with
components positioned as closely as possible. This particularly applies to FET gate,
sense and kelvin lines.
17.1.3 Connector decoupling
Decoupling capacitors should be fitted directly on, or as close as possible to, connectors,
preventing currents being induced on FET or control tracks.
17.1.4 Module supply decoupling
This supply can be decoupled for EMC with a small ferrite bead.
Circuit analysis should include assessment of possible paths for EMC-induced currents
from different wiring harnesses connected to the PCB.
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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