BUK3F00-50WDXX Datasheet, PDF (15/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
MCSN
MASTER
MDO
MDI
SCSN
SLAVE1
SDI
SDO
SCSN
SLAVE2
SDI
SDO
SCSN
SLAVE3
SDI
SDO
001aag750
Fig 6. Daisy chain connection of three ASICs (requires three SPI 16-bit word cycles)
9.3.3 SPI watchdog
The SPI watchdog detects if there is a breakdown in the SPI communication with the
controller. A timer is activated that resets when a valid communication is received. If no
valid SPI communications are received within the specified time-out period, the watchdog
will signal this to the control logic.
The SPI watchdog is enabled either by setting pin WDEN = HIGH or by enabling
watchdog active with bit WD_TO[5]. FET channels can be turned either on or off when a
watchdog time-out occurs as set by register CHAN_WD_MAP. Pin WDTON is set LOW for
a selectable period when a watchdog time-out occurs and can be used as a reset for the
controller. An interrupt on pin INTN can also be set when a watchdog time-out occurs.
Other functions of the device are not changed in Watchdog mode. In particular, if the SPI
fault that caused the condition is resolved, SPI communication would work and
diagnostics could be performed.
See Section 11.1 “Reset for interrupt and SPI watchdog” for details of clearing watchdog
states.
Table 6. Select channel watchdog behavior register (address 0Ch) bit description
Address Register
Bit Description
0Ch
CHAN_WD_MAP^[1] 7 to 0 behavior when watchdog time-out occurs in individual
channels 7 to 0:
1 = turn selected channel on^[2]
0 = turn selected channel off
[1] A metal mask option WRITE_PROTECT is available, which means that registers are write protected.
[2] Provided channel is not mapped to a direct input pin. If channel is mapped to a direct input pin, then the
channel will only turn on if the direct input pin is HIGH.
Table 7. Watchdog time-out period setting register (address 0Dh) bit description
Address Register
Bit Description
0Dh
WD_TO
7 to 6 not used
5
enable watchdog
4 to 0 watchdog time-out period; see Table 8
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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