BUK3F00-50WDXX Datasheet, PDF (29/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 21. Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description …continued
Address Register
Bit
Description
Bit latches
32h
ISR
interrupt status
[5]
15
channel overtemperature
[6][7] _yes
14
logic reset has occurred
[8] _yes
13
channel tripped by controller (low battery)
[8][12] _yes
12
V_BAT too low
11
charge pump fault
[8] _yes
[8] _yes
10
watchdog time-out
[9] _yes
9
wrong number of bits in SPI communication
[10] _yes
8
invalid address in SPI communication
[10] _yes
7 to 5 channel index generating interrupt (binary number)
[6] _yes
4
channel tripped by overcurrent
[6][11][12] _yes
3
channel tripped by overtemperature
[6][7] _yes
2
channel overcurrent
[6][11][13] _yes
1
channel open-circuit
[6][14] _yes
0
channel temperature sensor diode open-circuit
[6][15] _yes
33h
VERSION
device version number
15 to 8 main version
[16]
7 to 0 sub-version code
[17]
34h
DIAG_CHAN_01
high-side FET on-state and open-circuit detection
15 to 8 high-side FET in on-state for channels 7 to 0
[18]
7 to 0 high-side FET open-circuit detected on channels 7
[18]
to 0
35h
DIAG_CHAN_02
TSNSOPEN and overtemperature detection states
15 to 8 value of TSNSOPEN signal for channels 7 to 0
7 to 0 not used
38h to 3Fh DIAG_DETAIL_CHn
detail diagnostics channels 7 to 0
15 to 8 digital current measurement
7
channel temperature sensor open-circuit
[18] _yes
6
open-circuit load detected
[18] _yes
5
not used
4
channel overcurrent
[13][18] _yes
3
channel overtemperature
[18] _yes
2
channel tripped by controller (low battery)
[18] _yes
1
shorted output to V_BAT
0
channel requested by user
[18] _yes
[1] Values for each channel are (in priority order):
00 = no controller fault.
10 = channel selected (normal or PWM). Applies during the PWM period when the channel and PWM are both selected.
01 = channel not selected but controller fault (low battery). This is latched, only cleared by reading DIAG_CTRL or selecting channel.
11 = channel selected but tripped off. Applies when the channel is selected but tripped by overcurrent or overtemperature.
[2] Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided SPI fault is mapped to INTN).
[3] Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided controller fault is mapped to INTN).
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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