BUK3F00-50WDXX Datasheet, PDF(10/52 Page) NXP Semiconductors

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BUK3F00-50WDXX Datasheet, PDF (10/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

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NXP Semiconductors

BUK3F00-50WDxx

Controller for TrenchPLUS FETs

Table 5. User-accessible registers

Description

Mask Version default value[2]

option FE

FM FY

Read/write registers[3]

01h

CHAN_ONOFF

channels select: on/off; see Section 9.5.7

00h 00h 00h

02h

IN02_MAP

direct input pins IN0 and IN2 mapping;

see Section 9.5.8

Y[4] 21h 10h 1Ch

03h

IN13_MAP

direct input pins IN1 and IN3 mapping;

see Section 9.5.8

Y[4] 84h 40h 01h

04h

INP_MAP

PWM input pin INP mapping;

see Section 9.5.8

Y[4] 10h 08h 00h

05h

ANDOR_MAP

direct input pin AND/OR operation;

see Section 9.5.8

Y[4] 00h 00h 00h

06h

CURR_MEAS

channel select analog current measurement; N

see Section 9.4.2

00h 00h 00h

07h

SEL_CURR_TRIP_

select current tripping channel;

CHAN

see Section 9.5.2

Y[4] 00h 00h 00h

08h

CHAN_OT_FAULT_CLR channel set overtemperature fault clear;

Y[4] 00h 00h 00h

see Section 9.5.1

09h

PWM_SYNC

channel PWM synchronization;

see Section 9.3.4

00h 00h 00h

0Ah

PWM_SAM_BEGINEND channel PWM sample point begin or end;

FFh FFh FFh

see Section 9.3.4

0Ch

CHAN_WD_MAP

select channel watchdog behavior;

see Section 9.3.3

Y[4] 21h 58h 1Dh

0Dh

WD_TO

watchdog time-out period setting;

see Section 9.3.3

Y[4] 3Fh 3Fh 3Fh

0Eh

CTRL_SET

controller settings; see Section 9.5.5

Y[4] 08h 08h 08h

0Fh

INT_PWM_FREQ

internal PWM frequency setting;

see Section 9.3.4

Y[4] B6h BBh B1h

10h

PWM_DC_CH0

internal PWM duty cycle setting for channel 0 Y[4][5] FFh FFh FFh

11h

PWM_DC_CH1

internal PWM duty cycle setting for channel 1; Y[4][5] FFh FFh FFh

see Section 9.3.4

12h

PWM_DC_CH2

internal PWM duty cycle setting for channel 2; Y[4][5] FFh FFh FFh

see Section 9.3.4

13h

PWM_DC_CH3

internal PWM duty cycle setting for channel 3; Y[4][5] FFh FFh FFh

see Section 9.3.4

14h

PWM_DC_CH4

internal PWM duty cycle setting for channel 4; Y[4][5] FFh FFh FFh

see Section 9.3.4

15h

PWM_DC_CH5

internal PWM duty cycle setting for channel 5; Y[4][5] FFh FFh FFh

see Section 9.3.4

16h

PWM_DC_CH6

internal PWM duty cycle setting for channel 6; Y[4][5] FFh FFh FFh

see Section 9.3.4

17h

PWM_DC_CH7

internal PWM duty cycle setting for channel 7; Y[4][5] FFh FFh FFh

see Section 9.3.4

18h

OT_TRIPLEV_CH30

overtemperature trip level channels 3 to 0;

Y[4] AAh AAh AAh

see Section 9.5.1

BUK3F00-50WDXX_4

Product data sheet

Rev. 04 â 4 September 2008

10 of 52

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