BUK3F00-50WDXX Datasheet, PDF (20/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
9.5.2 Overcurrent protection
The overcurrent protection on each channel allows for high inrush currents. This
protection also allows for turn-on or transient low battery conditions that can occur with
the configuration of high-side FET switches. Delay time in operating overcurrent protection
is determined by the actual FET.
For high-side switches, FET turn-on is determined when the sense voltage exceeds the
low sense threshold voltage (V_th(sense)low), within 40 µs (nominal), and when the
battery-to-kelvin voltage exceeds the on-state threshold voltage between battery and pin
KELVIN (V_{th(on)(bat-KEL)}).
The following overcurrent protection is available:
Turn-on overcurrent trip (TONOCH) — For channels configured as high-side switches.
Operates during FET turn-on or transient low battery conditions. The threshold level is a
set multiple of I_{meas(ADC)(fs)} × (I_IREFCURR / 50 µA). This is simplified when I_IREFCURR =
50 µA. For low current sense voltage (< 2.5 V) the trip level is below the specified multiple
of I_{meas(ADC)(fs)}. This protection cannot be disabled.
Overcurrent high trip (OCH) — For channels configured as high-side switches. This
does not operate during FET turn-on or transient low battery conditions. The threshold
level is a set multiple of I_{meas(ADC)(fs)} × (I_IREFCURR / 50 µA). This is simplified when
I_IREFCURR = 50 µA. This protection cannot be disabled or delayed.
Overcurrent low trip (OCL) — Operates at set currents of the ADC output up to
I_{meas(ADC)(fs)} with the ADC measurement accuracy. The threshold level is set by register
CURR_TRIPLEV_CHn. This protection can be disabled or delayed.
Table 13. FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit
description
Address Register
Bit Description
07h
SEL_CURR_TRIP_CHAN^[1] 7 to 0 select current tripping for OCL in individual
channels 7 to 0:
1 = selected
0 = not selected
1Ah
IFSC_CH30^[1]
set I_{meas(ADC)(fs)} data bits in channels 3 to 0 to
one of four current trip levels:
00 = 0.5 mA
01 = 1.0 mA
10 = 1.5 mA
11 = 2.0 mA
7, 6 set channel 3 full-scale current bits 1 and 0
5, 4 set channel 2 full-scale current bits 1 and 0
3, 2 set channel 1 full-scale current bits 1 and 0
1, 0 set channel 0 full-scale current bits 1 and 0
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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