BUK3F00-50WDXX Datasheet, PDF (26/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
10. Fixed functional settings
A number of settings are fixed mask options. These settings do not have a register
address and cannot be read or changed by the user.
Table 19. Protected settings
Name
Bit
Description
DIG_OLTH
DIG_FET
CHAN_ALLOW_RETRY
RETRY_SETTINGS
WRITE_PROTECT
open-circuit threshold level; 8-bit register
7 to 4 not applicable
3 to 0 high side: (0000) b3, b2, b1, b0
channel tripping behavior and filter times
8, 7 t_low(bat) setting:
00/11 = 128 µs (min) to 144 µs (max)
01 = 256 µs (min) to 288 µs (max)
10 = 512 µs (min) to 576 µs (max)
6, 5 t_high(bat) setting:
00/11 = 16 µs (min) to 20 µs (max)
01 = 32 µs (min) to 40 µs (max)
10 = 64 µs (min) to 80 µs (max)
4
high-side channels on low V_BAT:
1 = no trip
0 = trip
3, 2 trip channel output filter time:
00 = immediate
1, 0 TONOCH filter time (in turn-on state):
00 = immediate
01 = 1.0 µs
10 = 1.5 µs
11 = 2.0 µs (min) to 3.0 µs (max)
7 to 0 allow trip and retry after OCH, TONOCH or OCL faults select
channels 7 to 0:
1 = allowed
0 = not allowed
trip retry delay and number of retries
4, 3 wait time before retry:
00 = 64 µs (min) to 128 µs (max)
01 = 192 µs (min) to 256 µs (max)
10 = 320 µs (min) to 384 µs (max)
11 = 448 µs (min) to 512 µs (max)
2 to 0 number of retries, set binary number
0
write protect (registers WD_TO and CHAN_WD_MAP)^[1]:
1 = no write access
0 = write access
Version setting
values
FE FM FY
23h 23h 23h
0C1h 0C1h 0C1h
FFh FFh FFh
1Bh 1Bh 1Bh
1b 1b 1b
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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