BUK3F00-50WDXX Datasheet, PDF (24/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 18. Channel selection and pin mapping register (addresses 02h to 05h) bit
description …continued
Address Register
Bit
Description
05h
ANDOR_MAP^[1]
direct input pin AND/OR operation
7 to 4 direct input AND/OR operation for individual
channels 7 to 4:
1 = pin IN2 AND pin IN3
0 = pin IN2 OR pin IN3
3 to 0 direct input AND/OR operation for individual
channels 3 to 0:
1 = pin IN0 AND pin IN1
0 = pin IN0 OR pin IN1
[1] A metal mask option WRITE_PROTECT is available, which means that these registers are reloaded with
the default value if an SPI watchdog time-out occurs.
[2] In Watchdog mode; pins IN0 to IN3 reset channel faults (such as short-circuit) when the pin is set to LOW;
Pin INP does not reset channel faults. Hence, it is not recommended that an external PWM signal is
connected to pins IN0 to IN3 for normal operation.
9.5.9 FET channel on/off control
Each FET channel can be switched by a request from different sources, the logical
relationship between these sources is shown in Figure 7.
IN0,IN2
IN1,IN3
INP
CHAN_ONOFFn
IN02_MAPn
IN13_MAPn
ANDOR_MAPn
INP_MAPn
watchdog
timeout
PWM_DC_CHn
1
0
DIAG_DETAIL_CH0
0
ONn
1
CHAN_WD_MAPn
Fig 7. FET channel on/off request logic
001aaf053
9.5.10 Power dissipation
The FET interface comprises a significant part of the BUK3F00-50WD thermal budget.
The dissipation is caused by the regulation of the SENSE pin voltage while sinking the
sense current. The dissipation, per channel, can be estimated from the product of I_SENSE
and V_BAT. Special care should be taken at high battery voltages that the power dissipation
does not cause the device to overheat.
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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