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BUK3F00-50WDXX Datasheet, PDF (11/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs
NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Table 5. User-accessible registers …continued
Register[1] Name
Description
Mask Version default value[2]
option FE
FM FY
19h
OT_TRIPLEV_CH74
overtemperature trip level channels 7 to 4;
Y[4] AAh AAh AAh
see Section 9.5.1
1Ah
IFSC_CH30
full-scale reference current channels 3 to 0; Y[4] AAh FFh FFh
see Section 9.5.2
1Bh
IFSC_CH74
full-scale reference current channels 7 to 4; Y[4] AAh FFh FFh
see Section 9.5.2
1Ch
CURR_TRIPLEV_CH0 current trip level for channel 0;
see Section 9.5.2
N[4] FFh FFh FFh
1Dh
CURR_TRIPLEV_CH1 current trip level for channel 1;
see Section 9.5.2
N[4] FFh FFh FFh
1Eh
CURR_TRIPLEV_CH2 current trip level for channel 2;
see Section 9.5.2
N[4] FFh FFh FFh
1Fh
CURR_TRIPLEV_CH3 current trip level for channel 3;
see Section 9.5.2
N[4] FFh FFh FFh
20h
CURR_TRIPLEV_CH4 current trip level for channel 4;
see Section 9.5.2
N[4] FFh FFh FFh
21h
CURR_TRIPLEV_CH5 current trip level for channel 5;
see Section 9.5.2
N[4] FFh FFh FFh
22h
CURR_TRIPLEV_CH6 current trip level for channel 6;
see Section 9.5.2
N[4] FFh FFh FFh
23h
CURR_TRIPLEV_CH7 current trip level for channel 7;
see Section 9.5.2
N[4] FFh FFh FFh
24h
IRQ_MAP
interrupt request mapping; see Section 9.5.2 Y[4] 04h 19h 00h
25h
CURR_TRIP_
BLANKTIME
current trip blanking time; see Section 9.5.2 Y[4] 2Fh 2Fh 2Fh
26h
OLDET_ONOFF
off-state open-circuit detection;
see Section 9.5.6
N
FFh FFh FFh
27h
READBACK
register and diagnostic read back;
see Section 9.3.2
N
30h 30h 30h
28h
IRQ_CHAN_MAP
interrupt generating channels;
see Section 9.3.5
N[4] FFh FFh FFh
Write-only registers[6]
29h
CLEAR_CHAN_INTN clear channels and interrupt; see Section 11.1
2Ah
CLEAR_WD
clear watchdog state; see Section 11.1
Read-only registers[7]
30h
DIAG_BASIC
basic diagnostics; see Section 11.2
31h
DIAG_CTRL
controller diagnostics; see Section 11.2
32h
ISR
interrupt status register; see Section 11.2
33h
VERSION
device version number; see Section 11.2
34h
DIAG_CHAN_01
VOUTHIGH and VOUTLOW states[8];
see Section 11.2
35h
DIAG_CHAN_02
TSNSOPEN signal state[9]; see Section 11.2
38h
DIAG_DETAIL_CH0
detail diagnostics; channel 0; see Section 11.2
39h
DIAG_DETAIL_CH1
detail diagnostics; channel 1; see Section 11.2
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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