BUK3F00-50WDXX Datasheet, PDF (44/52 Pages) NXP Semiconductors – Controller for TrenchPLUS FETs

NXP Semiconductors
BUK3F00-50WDxx
Controller for TrenchPLUS FETs
17.3 Additional metal mask options
Additional metal mask options can be provided with different default settings. Table 35 can
be used to submit these requirements for assessment.
Table 35. Registers for mask options
Register Name
Description
02h
IN02_MAP
direct input pins IN0 and IN2 mapping
03h
IN13_MAP
direct input pins IN1 and IN3 mapping
04h
INP_MAP
PWM input pin INP mapping
05h
ANDOR_MAP
direct input pin AND/OR operation
07h
SEL_CURR_TRIP_CHAN select current tripping channel
08h
CHAN_OT_FAULT_CLR channel set overtemperature fault clear
0Ch
CHAN_WD_MAP
select channel watchdog behavior
0Dh
WD_TO
watchdog time-out period setting
0Eh
CTRL_SET
controller settings
0Fh
INT_PWM_FREQ
internal PWM frequency setting
10h
PWM_DC_CH0
internal PWM duty cycle setting for channel 0
11h
PWM_DC_CH1
internal PWM duty cycle setting for channel 1
12h
PWM_DC_CH2
internal PWM duty cycle setting for channel 2
13h
PWM_DC_CH3
internal PWM duty cycle setting for channel 3
14h
PWM_DC_CH4
internal PWM duty cycle setting for channel 4
15h
PWM_DC_CH5
internal PWM duty cycle setting for channel 5
16h
PWM_DC_CH6
internal PWM duty cycle setting for channel 6
17h
PWM_DC_CH7
internal PWM duty cycle setting for channel 7
18h
OT_TRIPLEV_CH30
overtemperature trip level channels 3 to 0
19h
OT_TRIPLEV_CH74
overtemperature trip level channels 7 to 4
1Ah
IFSC_CH30
full-scale reference current channels 3 to 0
1Bh
IFSC_CH74
full-scale reference current channels 7 to 4
24h
IRQ_MAP
interrupt request mapping
25h
CURR_TRIP_BLANKTIME current trip blanking time
-
DIG_OLTH
open-circuit threshold level
-
DIG_FET
channel tripping behavior and filter times
-
CHAN_ALLOW_RETRY
channel allow trip and retry after OCH or TONOCH faults
-
RETRY_SETTINGS
trip retry delay and number of retries
-
WRITE_PROTECT
write protect (registers WD_TO and CHAN_WD_MAP)
-
WDPN_LOW_TIME
watchdog time-out LOW time pulse (pin WDTON)
-
VSBATLOW_DEB_EN
debounce on V_BAT LOW signal
-
NXIFSC_CH0
channel 0 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
-
NXIFSC_CH1
channel 1 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
-
NXIFSC_CH2
channel 2 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
-
NXIFSC_CH3
channel 3 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
-
NXIFSC_CH4
channel 4 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
-
NXIFSC_CH5
channel 5 ratio OCH and TONOCH trip level to I_{meas(ADC)(fs)}
Setting required
BUK3F00-50WDXX_4
Product data sheet
Rev. 04 — 4 September 2008
© NXP B.V. 2008. All rights reserved.
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