MC68HC05J3 Datasheet, PDF (78/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table 9-6 AC electrical characteristics for 3.3V operation
(V_DD = 3.3 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H
Characteristic
Symbol
Min
Frequency of operation
Crystal
External clock
Internal operating frequency
f_OSC
—
f_OSC
dc
Crystal (f_OSC /2)
f_OP
—
External clock (f_OSC /2)
f_OP
dc
Processor cycle time
t_CYC
1000
Ceramic resonator start-up time
t_OXOV
—
Ceramic resonator STOP recovery start-up time t_ILCH
—
OSC1 pulse width
t_OH, t_OL
200
RESET pulse width
t_RL
1.5
16-bit timer
Resolution⁽¹⁾
t_RESL
—
Input capture pulse width
Input capture pulse period
t_TLTH
500
t_TLTL
(2)
Power-on reset delay
t_PORL
4064
Interrupt pulse width low (edge-triggered)
Interrupt pulse period (see Figure 9-2)
t_ILIH
250
t_ILIL
(3)
Max
Unit
2.1
MHz
2.1
MHz
1.05
MHz
1.05
MHz
—
ns
20
ms
20
ms
—
ns
—
t_CYC
4
t_CYC
—
ns
—
t_CYC
4064
t_CYC
—
ns
—
t_CYC
(1) Since the 2-bit prescaler in the timer must count four external cycles (t_CYC), this is the limiting factor in
determining the timer resolution.
(2) The minimum period t_TLTL should not be less than the number of cycles it takes to execute the capture
interrupt service routine plus 24 t_CYC.
(3) The minimum period t_ILIL should not be less than the number of cycles it takes to execute the interrupt
service routine plus 21 t_CYC.
9
IRQ
t_ILIH
t_ILIL
Edge-sensitive trigger — The minimum t_ILIH is either 125ns (V_DD=5V) or 250ns (V_DD=3.3V). The minimum period
t_ILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 t_CYC.
Edge and level sensitive trigger — If IRQ remains low after the initial interrupt is serviced, the MCU recognises the
interrupt until the IRQ line returns to a high level.
Figure 9-2 External interrupt timing
MOTOROLA
9-6
ELECTRICAL SPECIFICATIONS
TPG
MC68HC05J3