MC68HC05J3 Datasheet, PDF (32/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

4.4
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.4.1 Port A data register (PORTA)
4
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
A data direction register (DDRA).
The state of the bits in the port data register following reset is undefined.
4.4.2 Port B data register (PORTB)
Port B data (PORTB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0001 0
0
Undefined
In addition to the normal port functions, port B is equipped with a keyboard interrupt capability as
described in Section 4.3. Two of the port pins (PB4 and PB5) are shared with the TCMP and TCAP
pins respectively. These functions are controlled using the port B configuration register.
4.4.3 Port B configuration register (CONFB)
Port B configuration (CONFB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0007 KSF KIE TCAP TCMP 0
0
0
0 0000 0000
Reset clears this register, thus returning all port B pins to normal I/O lines.
KSF — Keyboard interrupt status flag
1 (set) – Keyboard interrupt has occurred.
0 (clear) – No keyboard interrupt has occurred.
MOTOROLA
4-4
INPUT/OUTPUT PORTS
TPG
MC68HC05J3