MC68HC05J3 Datasheet, PDF (51/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7
RESETS AND INTERRUPTS
7.1
Resets
The MC68HC05J3 can be reset in three ways: by the initial power-on reset function, by an active
low input to the RESET pin and by a COP watchdog reset, if the watchdog timer is enabled. Any
of these resets will cause the program to go to its starting address, specified by the contents of
memory locations $0FFE and $0FFF, and cause the interrupt mask of the condition code register
to be set.
7
t_VDDR
V_DD
V_DD threshold (1-2V typical)
t_OXOV
OSC1
t_PORL
t_CYC
Internal
processor clock
RESET
Internal
address bus
Internal
data bus
(Internal power-on reset)
t_RL(or t_DOGL) _{(External hardware reset)}
New
0FFE 0FFE 0FFE 0FFE 0FFF _PC
Reset sequence
New New Op
PCH PCL code
Program
execution
begins
0FFE 0FFE 0FFE 0FFE
0FFF
New
PC
Reset sequence
New New Op
PCH PCL code
Program
execution
begins
Figure 7-1 Reset timing diagram
MC68HC05J3
RESETS AND INTERRUPTS
TPG
MOTOROLA
7-1