MC68HC05J3 Datasheet, PDF (50/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Internal
processor clock
Internal
timer clocks
 _T00

 ^T01
 ^T10
 ^T11
16-bit
counter
Output compare
register
$F456
(Note 1)
CPU writes $F457
$F457
$F458
$F457
$F459
Compare register
latch
(Note 1)
6
Output compare
flag and TCMP
(Note 2)
Note:
(1) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
(2) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this
example).
Figure 6-4 Timer state timing diagram for output compare
Internal
processor clock
Internal
timer clocks
 _T00


T01
 ^T10
 ^T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared
by a read of the timer status register during the internal processor clock high time, followed by a read
of the counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
MOTOROLA
6-10
16-BIT PROGRAMMABLE TIMER
TPG
MC68HC05J3