MC68HC05J3 Datasheet, PDF (45/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

IEDG — Input edge
1 (set) – TCAP is positive-going edge sensitive.
0 (clear) – TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture register. When clear, a negative-going edge triggers the transfer.
OLV — Output level
1 (set) – A high output level will appear on the TCMP pin.
0 (clear) – A low output level will appear on the TCMP pin.
When OLV is set, a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP pin. When clear, it will be a low level that
will appear on the TCMP pin.
6
6.2.2 Timer status register – TSR
The Timer Status register ($13) contains the status bits for the above three interrupt conditions —
ICF, OCF, TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
Timer status (TSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0013 ICF OCF TOF 0
0
0
0
0 uuu0 0000
ICF — Input capture flag
1 (set) – A valid input capture has occurred.
0 (clear) – No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set. ICF is cleared by reading the TSR and
then the input capture low register at $15.
MC68HC05J3
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-5