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MC68HC05J3 Datasheet, PDF (37/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit | |||
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to the value in the core timer counter register/RTI divider, hence the actual COP timeout period
will vary between 7x and 8x the RTI period.
The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
COP timeout is prevented by writing a â0â to bit 0 of address $0FF0. When the COP is cleared, only
the ï¬nal divide-by-eight stage is cleared (see Figure 5-1).
5.3
Core timer registers
5
5.3.1 Core timer control and status register (CTCSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer control/status (CTCSR) $0008 CTOF RTIF CTOFE RTIE 0
0 RT1 RT0 uu00 0011
CTOF â Core timer overï¬ow
1 (set) â Core timer overï¬ow has occurred.
0 (clear) â No core timer overï¬ow interrupt has been generated.
This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request
will be generated if CTOFE is set. When set, the bit may be cleared by writing a â0â to it.
RTIF â Real time interrupt ï¬ag
1 (set) â A real time interrupt has occurred.
0 (clear) â No real time interrupt has been generated.
This bit is set when the output of the chosen stage becomes active; an interrupt request will be
generated if RTIE is set. When set, the bit may be cleared by writing a â0â to it.
CTOFE â Core timer overï¬ow enable
1 (set) â Core timer overï¬ow interrupt is enabled.
0 (clear) â Core timer overï¬ow interrupt is disabled.
Setting this bit enables the core timer overï¬ow interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set. Clearing this bit disables the core timer overï¬ow
interrupt capability.
MC68HC05J3
CORE TIMER
TPG
MOTOROLA
5-3
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