MC68HC05J3 Datasheet, PDF(56/92 Page) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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MC68HC05J3 Datasheet, PDF (56/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

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7.4

Non-maskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is

executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

generated after the SWI was fetched. The SWI interrupt service routine address is speciï¬ed by

the contents of memory locations $0FFC and $0FFD.

7.5

Maskable hardware interrupts

If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are

masked. Clearing the I-bit allows interrupt processing to occur.

Note: The internal interrupt latch is cleared in the ï¬rst part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the

I-bit is cleared.

7.5.1 External interrupt (IRQ or keyboard)

These external interrupt sources will vector to the same interrupt service routine, whose start

address is contained in memory locations $0FFA and $0FFB. IRQ can be selected to be either

edge sensitive or edge-and-level sensitive. Further details of the keyboard interrupt facility can be

found in Section 4.3.

7.5.2 Core timer interrupts

There are two core timer interrupt ï¬ags that cause an interrupt whenever an interrupt is enabled

and its ï¬ag becomes set (RTIF and CTOF). The interrupt ï¬ags and enable bits are located in the

core timer control and status register (CTCSR). These interrupts vector to the same interrupt

service routine, whose start address is contained in memory locations $0FF8 and $0FF9. Full

details of the core timer can be found in Section 5.

To make use of the real time interrupt, the RTIE bit must ï¬rst be set. The RTIF bit will then be set

after the speciï¬ed number of counts.

To make use of the core timer overï¬ow interrupt, the CTOFE bit must ï¬rst be set. The CTOF bit

will then be set when the core timer counter register overï¬ows from $FF to $00.

MOTOROLA

7-6

RESETS AND INTERRUPTS

TPG

MC68HC05J3

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