MC68HC05J3 Datasheet, PDF (30/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Data direction
register bit
DDRn
Latched data
DATA
Output
I/O
register bit
buffer
pin
DDRn DATA I/O Pin
O/P
data

1
0
0
4
buffer
Input
buffer
Output _
1

0
Input _
0
1
1
0
tristate
1
tristate
Figure 4-1 Standard I/O port structure
Table 4-1 I/O pin states
R/W DDRn
Action of MCU write to/read of data bit
0
0 The I/O pin is in input mode. Data is written into the output data latch.
0
1 Data is written into the output data latch, and output to the I/O pin.
1
0 The state of the I/O pin is read.
1
1 The I/O pin is in output mode. The output data latch is read.
4.2
Port A
This port is a standard M68HC05 bidirectional I/O port, comprising a data register and a data
direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
4.3
Port B
In addition to the standard port functions, this 6-bit port has a programmable keyboard interrupt
feature on pins PB0–PB3 and shares two pins (PB4 and PB5) with the timer subsystem. On reset,
this port is configured as a standard I/O port, comprising a data register and a data direction
register.
MOTOROLA
4-2
INPUT/OUTPUT PORTS
TPG
MC68HC05J3