MC68HC05J3 Datasheet, PDF (54/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on or external reset clear all interrupt enable bits thus preventing interrupts
during the reset sequence.
7.3.1 Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority first. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
7
Table 7-2 shows the relative priority of all the possible interrupt sources. Figure 7-2 shows
the interrupt processing flow.
Table 7-2 Interrupt priorities
Source
Register
Reset
—
Software interrupt (SWI)
—
External interrupt (IRQ)/
keyboard interrupt
—
CONFB
Core timer
CTCSR
16-bit timer – input capture TSR
16-bit timer – output compare TSR
16-bit timer – overflow
TSR
Reserved
—
Flags
—
—
—
PTBIF
CTOF, RTIF
ICF
OCF
TOF
—
Vector address
$0FFE, $0FFF
$0FFC, $0FFD
$0FFA, $0FFB
$0FF8, $0FF9
$0FF6, $1FF7
$0FF4, $0FF5
$0FF2, $0FF3
$0FF0, $0FF1
Priority
highest
MOTOROLA
7-4
RESETS AND INTERRUPTS
TPG
MC68HC05J3