MC68HC05J3 Datasheet, PDF (67/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Table 8-8 Instruction set (2 of 2)
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C
COM
• • ◊◊1
CPX
• • ◊◊◊
DEC
• • ◊◊ •
EOR
• • ◊◊ •
INC
• • ◊◊ •
JMP
•••••
JSR
•••••
LDA
• • ◊◊ •
LDX
• • ◊◊ •
LSL
• • ◊◊◊
LSR
• • 0◊◊
MUL
0• • •0
NEG
• • ◊◊◊
NOP
•••••
ORA
• • ◊◊ •
ROL
• • ◊◊◊
ROR
• • ◊◊◊
RSP
RTI
•••••
?????
8
RTS
•••••
SBC
• • ◊◊◊
SEC
• • • •1
SEI
•1• • •
STA
• • ◊◊ •
STOP
•0• • •
STX
• • ◊◊ •
SUB
• • ◊◊◊
SWI
•1• • •
TAX
•••••
TST
• • ◊◊ •
TXA
•••••
WAIT
•0• • •
Address mode abbreviations
BSC Bit set/clear
IMM Immediate
BTB Bit test & branch
IX Indexed (no offset)
DIR Direct
IX1 Indexed, 1 byte offset
EXT Extended
IX2 Indexed, 2 byte offset
INH Inherent
REL Relative
Not implemented
Condition code symbols
H Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
I Interrupt mask
• Not affected
N Negate (sign bit)
? Load CCR from stack
Z Zero
0 Cleared
C Carry/borrow
1 Set
MC68HC05J3
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
8-9