MC68HC05J3 Datasheet, PDF (38/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

RTIE — Real time interrupt enable
1 (set) – Real time interrupt is enabled.
0 (clear) – Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set. Clearing this bit disables the real time interrupt capability.
RT1:RT0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to
alter them if necessary. The COP reset times are also determined by these two bits. Care should
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be taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain.
If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems, the COP should be cleared
before changing the RTI taps. See Table 5-1 for some example RTI periods.
Table 5-1 Example RTI periods
RT1
RT0
Division
ratio
00
2¹⁴
01
2¹⁵
10
2¹⁶
11
2¹⁷
Bus frequency
f_OP = 2 MHz
RTI
period
Minimum
COP
period
8.2ms 57.3ms
16.4ms 114.7ms
32.8ms 229.4ms
65.5ms 458.8ms
5.3.2 Core timer counter register (CTCR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
Core timer counter (CTCR) $0009
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain. Reset clears this register.
MOTOROLA
5-4
CORE TIMER
TPG
MC68HC05J3