MC68HC05J3 Datasheet, PDF (59/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

8
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05J3.
8.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 8-1. The interrupt
stacking order is shown in Figure 8-2.
7
0
Accumulator
7
0
Index register
8
15
7
0
Program counter
15
7
0
0000000011
Stack pointer
7
0
1 1 1 H I N Z C Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
Figure 8-1 Programming model
7
Increasing
memory
address
Unstack
Condition code register
Accumulator
Index register
Program counter high
Program counter low
0 ^Stack
Decreasing
memory
address
Figure 8-2 Stacking order
MC68HC05J3
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
8-1