MC68HC05J3 Datasheet, PDF (53/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.2
Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the
execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.
Table 7-1 shows the resulting action of any type of system reset, but not necessarily in the order
in which they occur.
Table 7-1 Effect of RESET, POR, STOP and WAIT
Function/effect
RESET POR WAIT STOP
16-bit timer prescaler set to zero
x
x
-
-
16-bit timer counter set to $FFFC
x
x
-
-
All timer enable bits cleared (disable)
x
x
-
-
Data direction registers cleared (inputs)
x
x
-
-
Stack pointer set to $00FF
x
x
-
-
Force internal address bus to restart
x
x
-
-
Vector $0FFE, $0FFF
x
x
-
-
Interrupt mask bit (I-bit in CCR) set
Interrupt mask bit (I-bit in CCR) cleared
x
x
-
-
-
-
x
x
7
Reset STOP latch
x
x
-
-
Reset IRQ latch
x
x
-
-
Reset WAIT latch
x
x
-
-
Oscillator disabled for 4064 cycles
-
x
-
x
Timer clock cleared
-
x
-
x
Watchdog counter reset
x
x
x
x
7.3
Interrupts
The MCU can be interrupted by four different sources, three maskable hardware interrupts and
one non-maskable software interrupt:
• External signal on the IRQ pin
• Core timer
• 16-bit programmable timer
• Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (ReTurn from Interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the
corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled.
MC68HC05J3
RESETS AND INTERRUPTS
TPG
MOTOROLA
7-3