MC68HC05J3 Datasheet, PDF (57/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

7.5.3 16-bit timer interrupts
There are three different timer interrupt flags (ICF, OCF and TOF) that will cause a timer interrupt
whenever they are set and enabled. These three interrupt flags are found in the three most
significant bits of the timer status register (TSR) at location $13. ICF will vector to the service
routine defined by $0FF6 - $0FF7, OCF will vector to the service routine defined by $0FF4 - $0FF5
and TOF will vector to the service routine defined by $0FF2 - $0FF3 as shown in Table 7-2.
There are three corresponding enable bits; ICIE, OCIE and TOIE which are located in the timer
control register (TCR) at address $12. Full details of the programmable timer can be found in
Section 6.
7.6
Hardware controlled interrupt sequence
The following three functions; reset, STOP and WAIT, are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
Figure 2-4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
7
in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
STOP: The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’
until an external interrupt (IRQ) or a keyboard interrupt occurs or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt
(IRQ or keyboard) or a timer interrupt. There are no special WAIT vectors for these
individual interrupts.
MC68HC05J3
RESETS AND INTERRUPTS
TPG
MOTOROLA
7-7