MC68HC05J3 Datasheet, PDF (23/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

2.3
Low power modes
2
2.3.1 STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog
timer) operation.
During STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits
(CTOFE and RTIE) in the CTCSR, the timer flags for the 16-bit timer in the TSR register and the
interrupt enable bits in the TCR register are cleared by internal hardware. This removes any
pending timer interrupt requests and disables any further timer interrupts. The timer prescaler is
cleared. The I-bit in the CCR is cleared to enable external interrupts. All other registers, the
remaining bits in the CTCSR, and memory contents remain unaltered. All input/output lines
remain unchanged. The processor can be brought out of STOP mode only by an external interrupt,
a keyboard interrupt, if enabled, or a reset (see Figure 2-4).
2.3.2 WAIT
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended, but the 16-bit timer and
the core timer remain active. An external or keyboard interrupt or an interrupt from either of the
timers, if enabled, will cause the MCU to exit WAIT mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory
and input/output lines remain in their previous state. The 16-bit timer or the core timer interrupts
may be enabled to allow a periodic exit from WAIT mode. See Figure 2-4.
MC68HC05J3
MODES OF OPERATION AND PIN DESCRIPTIONS
TPG
MOTOROLA
2-7