MC68HC05J3 Datasheet, PDF (47/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

transition. The level transition that triggers the counter transfer is defined by the input edge bit
(IEDG). The most significant 8 bits are stored in the input capture high register at $14, the least
significant in the input capture low register at $15.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronisation. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register on each valid signal transition whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds to the
most recent input capture. After a read of the input capture register MSB ($14), the counter
transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the
input capture software routine and its interaction with the main program to determine the minimum
pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since the two actions occur on opposite edges of the internal bus clock.
The contents of the input capture register are undefined following reset.
6
6.2.5 Output compare function
‘Output compare’ is a technique that may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
6.2.6
Output compare high register
Output compare low register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high (OCH) $0016 (bit 15)
(bit 8) Undefined
Output compare low (OCL) $0017
Undefined
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register are continually compared with the
contents of the free-running counter and, if a match is found, the output compare flag (OCF) in the
timer status register is set and the output level (OLV) bit clocked to the output level register. The
output compare register values and the output level bit should be changed after each successful
comparison to establish a new elapsed timeout. An interrupt can also accompany a successful
output compare provided the corresponding interrupt enable bit (OCIE) is set. (The free-running
counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
MC68HC05J3
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-7