MC68HC05J3 Datasheet, PDF (39/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

5.4
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains active. If the CTIMER
interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (t_PORL). The timer is then cleared and operation resumes.
5
MC68HC05J3
CORE TIMER
TPG
MOTOROLA
5-5