MC68HC05J3 Datasheet, PDF (36/92 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09.
A timer overflow function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of f_OP/1024. (The POR signal (t_PORL) is also derived from this register, at
f_OP/4064.) The counter register circuit is followed by four more stages, with the resulting clock
(f_OP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages
with a 1-of-4 selector. The output of the RTI circuit is further divided by 8 to drive the COP
watchdog timer circuit. The RTI rate selector bits, and the RTI and CTIMER overflow enable bits
and flags, are located in the CTIMER control and status register (CTCSR) at location $08.
CTOF (core timer overflow flag) is a clearable, read-only status bit and is set when the 8-bit ripple
5
counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set.
Clearing the CTOF is done by writing a ‘0’ to it. Writing a ‘1’ to CTOF has no effect on the bit’s
value. Reset clears CTOF.
When CTOFE (core timer overflow enable) is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f_OP/4 and can
be used for various functions including a software input capture. Extended time periods can be
attained using the CTIMER overflow function to increment a temporary RAM storage location
thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the counter. After t_PORL
cycles, the power-on reset circuit is released, which again clears the counter chain and allows the
device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up
from zero and normal device operation will begin. When RESET is asserted at any time during
operation (other than POR), the counter chain will be cleared.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock
frequency that drives the RTI circuit is f_OP/2¹⁴ (or f_OP/16384), with three additional divider stages,
giving a maximum interrupt period of 4 seconds at a bus frequency (f_OP) of 32kHz. Register details
are given in Section 5.3.
5.2
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output of the RTI circuit and
further dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is
seven times the RTI period. This is because the COP will be cleared asynchronously with respect
MOTOROLA
5-2
CORE TIMER
TPG
MC68HC05J3