MC68HC908JK1 Datasheet, PDF (46/210 Pages) Motorola, Inc – MC68HC908JK1

FLASH Memory (FLASH)
4.9 FLASH Block Protect Register
The FLASH Block Protect Register is implemented as an 8-bit I/O
register. The value in this register determines the starting address of the
protected range within the FLASH memory.
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 4-3. FLASH Block Protect Register (FLBPR)
BPR[7:1], bit-0 — FLASH Protection Register Bits [7:1]
These eight bits in FLBPR (bit-0 is always 0) represent bits [12:5] of
a 16-bit memory address. Bits [15:13] are logic 1s and bits [4:0] are
logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00, XX40, XX80,
or XXC0 within the FLASH memory.
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
$00–$60
The entire FLASH memory is protected.
$62 (0110 0010)
$EC40 (1110 1100 0100 0000)
$64 (0110 0100)
$EC80 (1110 1100 1000 0000)
$68 (0110 1000)
$ED00 (1110 1101 0000 0000)
and so on...
$DE (1101 1110)
$FBC0 (1111 1011 1100 0000)
$FE (1111 1110)
$FFC0 (1111 1111 1100 0000)
$FF
The entire FLASH memory is not protected.
Technical Data
46
FLASH Memory (FLASH)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA