MC68HC908JK1 Datasheet, PDF (157/210 Pages) Motorola, Inc – MC68HC908JK1

I/O Ports
Port D
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 12-3 summarizes the operation
of the port D pins.
Table 12-3. Port D Pin Functions
DDRD
Bit
0
PTD Bit
X⁽¹⁾
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Accesses
to DDRA
Read/Write
DDRD[7:0]
1
X
Output
DDRD[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
12.6.3 Port D Control Register (PDCR)
Accesses to PTD
Read
Pin
Pin
Write
PTD[7:0]⁽³⁾
PTD[7:0]
The Port D Control Register enables/disables the pull-up resistor and
slow-edge high current capability of pins PTD6 and PTD7.
Address: $000A
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
SLOWD7 SLOWD6 PTDPU7
Write:
Reset: 0
0
0
0
0
0
0
Figure 12-12. Port D Control Register (PDCR)
Bit 0
PTDPU6
0
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain,
high current output (25mA sink) of port pins PTD6 and PTD7
respectively. DDRx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
PTDPUx — Pull-up Enable
The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and
PTD7 respectively, regardless the status of DDRDx bit.
1 = Enable 5k pull-up
0 = Disable 5k pull-up
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
I/O Ports
Technical Data
157