MC68HC908JK1 Datasheet, PDF (33/210 Pages) Motorola, Inc – MC68HC908JK1

Memory
Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$002B
↓
$003B
Read:
Unimplemented Write:
ADC Status and Control ^{Read: COCO}
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
$003C
Register Write:
(ADSCR) _{Reset: 0}
0
0
1
1
1
1
1
$003D
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
Write:
Reset:
Indeterminate after reset
Read:
0
0
0
0
0
$003E
ADC Input Clock Register
(ADICLK)
Write:
ADIV2
ADIV1
ADIV0
Reset: 0
0
0
0
0
0
0
0
$003F
Read:
Unimplemented Write:
Read:
SBSW
$FE00
Break Status Register
(BSR)
Write:
R
R
R
R
R
R
R
See note
Reset:
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP ILOP ILAD MODRST LVI
0
$FE01
Reset Status Register
(RSR)
Write:
POR: 1
0
0
0
0
0
0
0
$FE02
Read:
R
R
R
R
R
R
R
R
Reserved Write:
Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
R
$FE03
Register Write:
(BFCR) _{Reset: 0}
Read: 0
IF5
IF4
IF3
0
IF1
0
0
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
Memory
Technical Data
33