MC68HC908JK1 Datasheet, PDF (145/210 Pages) Motorola, Inc – MC68HC908JK1

Analog-to-Digital Converter (ADC)
I/O Registers
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 11-4. ADC Data Register (ADR)
11.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-5. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 11-2
shows the available clock configurations. The ADC clock should be
set to approximately 1MHz.
MC68H(R)C908JL3 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
Technical Data
145